In the nanometer era, die areas are getting larger as the designs are getting more and more complex. In order to ensure the correctness of the implemented design, bigger layout databases needs to be ...

The significant burden of parasitics on the performance of post-layout verification forces design engineers to use additional techniques in order to match the requirements of next generation designs.

Reducing the layout-versus-schematic debug time while continuously delivering reliable, high-performance designs is a must for chip designers needing to meet tight tapeout deadlines and hopefully ...

The semiconductor technology simulation world is typically divided into device-level TCAD (technology CAD) and circuit-level compact modeling. Larger EDA companies provide high-level design simulation ...

Tachyum™ Inc. announced that it has reached another milestone in meeting its goal of volume production of the Prodigy Universal Processor in 2021 by achieving 96 percent of silicon designed and layout ...

As we work through the sub-20 nm design space, the interactions between and effects on devices that are near each other are becoming critical factors in achieving the desired electrical performance.

Not every die-inspection problem succumbs to emission microscopy. But more of today’s backside challenges are disappearing as CAD navigation software and the microscope join forces. Emission ...

The design specification is the most important step in the design flow as it details anything that needs to be considered or strict requirements that need to be met when designing the ASIC, these ...